- compMk1.jpg (105.87 KiB) Viewed 3697 times
Instruction set
Code: Select all
Immediate Addressing
Loadi cc 1 cc ; load constant (cc) into accumulator
Addi cc 2 cc ; add constant to the accumulator
Subi cc 3 cc ; subtract constant from the accumulator
Multi cc 4 cc ; multiply accumulator by the constant
Divi cc 5 cc ; divide accumulator by the constant
Direct Addressing -operand points to the address
Addd aa 6 aa ; add contents of aa to the accumulator
Subd aa 7 aa ; subtract contents of aa from accumulator
Multd aa 8 aa ; multiply accumulator by contents of aa
Divd aa 9 aa ; divide accumulator by contents of aa
Loadd aa 10 aa ; load contents of aa to the accumulator
Store aa 11 aa ; store accumulator to memory address aa
Program Control (Jumping and Branching)
Jump aa 12 aa ; start executing instruction at aa
BrNeg aa 13 aa ; Branch to aa if result negative
BrPos aa 14 aa ; Branch to aa if result positive
BrZer aa 15 aa ; Branch to aa if result 0
Clear >15 ; clear ALL registers (used by reset)
Notes: instructions (1-16) are identified by a Blue Print signal
Operands (i.e. cc, aa) are identified by a Data signal blueprint string https://drive.google.com/file/d/0B3I2uZ ... sp=sharing
Description of the operation
Computorio MK I is a simple computer that has 64 words of ROM. 64 words of RAM, and can execute 16 instructions @ about 6/second (although I have hopes!)
So what are the different parts to it and how do they work.
Starting with the simplest, look at the bottom part of the picture. You will see 4 columns of combinators.
The ones with the constant combinators are the ROM. Each word of ROM consists of a constant and a decider used to address it.
The constant holds instructions (in the form of blueprint signal) and an operand (in the form of D signal).
The operand can be a constant or address. For example Blueprint1, D1 stand for "load accumulator with 1"
The decider next to the constant is of the form A=nnn; everything = count. In other words whenever Annn is present the decider will pass through its instruction and operand.
Each RAM word consists of 3 deciders. The one on the left is used for writing, the one in the center, stores the data, and the decider on the right reads it out. The decider on the left is of the form C=nnn (i.e. C signal is used to select the write address) whereas the one on the right is same as the ROM decider (except for the actual address). The center decider is a simple counter . This works because the write cycle is 2 ticks wide. During tick 1 RED signal (that zeroes the counter) is asserted. During tick 2 the actual data to be written is presented.(as the saying goes. "Timing is Everything").
Right above the RAM we find the Program Control Unit (PCU). It has two registers (once again simple counters) called Program Counter (PC) and Data Register (DR).
Program counter is incremented each instruction unless a Reset or a Branch/Jump is indicated. In case of Reset, PC will be hard loaded with a reset address (in this case 128). In case of Branch/Jump a DR (which keeps a copy of the operand (i.e. D signal) and the current address (A signal) will generate an offset between the desired address and the current address and sneakily add it to the PC.In case of direct address instructions, such as Load from memory address nnn, DR will seize address bus from the PC and present it's copy of the operand as an address.
Right above and to the left of the PCU we find the Instruction Decoder (ID). For those familiar with such things, it is of the microcode type and has two main parts. Part 1 (two columns of ROM on the left) contains timing signals for all the instructions. Each instruction may require that registers be zeroed out, loaded, or that certain data paths be enabled/disabled. Previously I made DR to be some kind of villain, molesting poor hapless PC, but in fact the signals are making all the decisions.
If you inspect any word in the ID, you may find a signal such as handgun (which zeroes PC) or yellow inserter (which loads it). The actual instruction may have half a dozen or more of such signals. Each signal will have a value. That value indicates on which tick of the clock the signal will be made active.(the clock is a simple counter counting from 1..n)
The activation of the signals is performed in the second part of the ID where we have 32 deciders each having a form of "signal=clock; signal= count".
To the right of the ID we find the Arithmetic Logic Unit (ALU).
ALU has three registers A,A2, and Status. A register is loaded with data coming in from the memory of with results of the operation (i.e. +-*/). The operation is performed with the assistance of A2 (copy of A) which provides the other operand while A is busy. Status register will store the type of result (i.e. <0.>0,=0) in the forms of flags which can be used in subsequent branch operations (and the dastardly DR).
In case you decide to build one of your own, you will probably want to know how to reset it and how to program it.
Programming is easy (ha!) , 16 instructions detailed in the attachment.
As for reset, if you look just below the ID, you will find 2 deciders and 2 constants. The first constant has bluepring16 , used during reset.
The second constant is currently empty. To reset the computer, insert GREEN signal for a short while then remove it.
As long as GREEN is present, the PC will stay at 128. Once Green is gone , the PC will start executing instruction at address 128.
I hope the above has been of some help in understanding.
Any questions or comments are always welcome.